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A thermal via is a small plated hole drilled through the PCB beneath a hot component pad, giving heat a low-resistance copper path to a ground plane, internal copper layer, or a heatsink on the other side of the board — instead of having to spread sideways through the poorly-conductive FR4. Each via behaves like a thermal resistor: θvia = L/(kcu×Abarrel), where L is the via length (board thickness) and Abarrel is the cross-sectional area of copper in the annular plated wall (or the full hole if filled). Multiple vias act as parallel thermal resistors, so an array of N identical vias has combined resistance θvia/N.
| Quantity | Formula |
|---|---|
| Annular barrel area (hollow) | A = π/4 × (ddrill² − (ddrill−2t)²) |
| Single via thermal resistance | θvia = L / (kcu × A) |
| N vias in parallel | θarray = θvia / N |
| Copper thermal conductivity | kcu ≈ 385 W/(m·K) |
Because copper conducts heat roughly 400× better than the FR4 substrate (about 0.3 W/m·K), even a small array of vias dramatically lowers the thermal path resistance under a hot device — which is why via arrays under power ICs, MOSFETs and LED pads are standard practice. This via-array resistance then adds in series with any other thermal path stages when computing overall junction temperature.
It is a small plated hole drilled through a PCB under a hot component to conduct heat vertically through the copper-plated barrel to a plane or layer on the other side, instead of relying on the poorly-conductive fibreglass substrate.
θvia = L/(kcu×A), where L is the via length (board thickness), kcu is copper's thermal conductivity (about 385 W/m·K), and A is the cross-sectional copper area of the plated barrel.
Vias in a thermal array act like resistors in parallel: N identical vias give a combined resistance of θvia/N. This is why designers use arrays of many small vias rather than one large one.
Drilling constraints and cost favour standard small via sizes, and using many vias spreads the thermal (and mechanical) connection more evenly across the pad, generally giving better and more reliable heat spreading than a single larger hole.
It is the thickness of copper deposited on the drilled hole wall (typically 20–35 µm). Since heat flows through this annular copper, thicker plating directly increases the cross-sectional area and lowers thermal resistance.
Filling with thermally-conductive epoxy (or plating solid copper) uses the entire via cross-section instead of just the thin annular wall, substantially lowering thermal resistance — often used for the highest-power designs, at extra manufacturing cost.
Thermal resistance is directly proportional to via length (board thickness), so a thinner board gives a shorter, lower-resistance thermal path — one reason very high-power modules sometimes use thin or metal-core boards.
Many QFN/DFN power ICs recommend a grid of small vias (often 0.3–0.33 mm diameter) spaced across the exposed thermal pad, connecting it to an internal or bottom-side copper plane or heatsink area.
Vias must be spaced to avoid solder wicking issues during reflow (too close can cause solder voiding) while staying within the pad area for maximum coverage; manufacturers publish recommended via patterns for common packages.
The via array's resistance adds in series with the other stages (junction-to-case, case-to-board, plane spreading, board-to-ambient), so its result plugs directly into the θCS or θSA term of a Junction Temperature calculation.
Copper's thermal conductivity (about 385 W/m·K) is roughly 1000× that of FR4 (about 0.3 W/m·K), so even a small amount of via copper dramatically outperforms conduction through the bare board material.
It models the vertical (through-board) conduction resistance of the vias themselves. Real designs also involve lateral spreading in the copper planes and convection/radiation to ambient, which are typically handled by simulation or the overall junction-to-ambient measurement for a full picture.
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