A plated via is, electrically, a very short, very wide, tube-shaped "trace" standing on its end. The same physics that limits a horizontal copper trace — I²R heating raising the temperature until it reaches a steady-state balance with the surroundings — applies to the plated copper barrel of a via. The standard engineering approach (used across the PCB industry) is to treat the via's annular copper cross-section exactly like a trace cross-section in the IPC-2221 current formula: I = k×ΔT0.44×A0.725, using the barrel's copper area in place of a trace's width×thickness.
A via's copper is only the thin plated wall of the drilled hole, not the whole hole cross-section (unless it is deliberately filled). For a typical 0.3 mm via with 25 µm plating, the annular wall area works out to be quite modest — which is why a single small via carries surprisingly little current (often just over an amp) and why designers use arrays of several vias in parallel under high-current pads, exactly as recommended for thermal vias.
| Quantity | Formula |
|---|---|
| Annular barrel area | A = π/4 × (ddrill² − (ddrill−2t)²) |
| Single-via current capacity | Ivia = k × ΔT0.44 × A0.725 |
| N vias in parallel | Itotal ≈ N × Ivia |
| k (used for via barrels) | 0.048 (treated like an external/exposed cross-section) |
Note the important distinction from the Thermal Via calculator: that tool finds a via array's thermal resistance for spreading heat vertically away from a hot component (a cooling problem). This calculator finds how much electrical current the via's own copper can carry without the via itself overheating (a current-carrying problem). They use the same physical via geometry but answer two different design questions.
It depends on the via's drill diameter, plating thickness, and how much temperature rise you allow, but a typical small via (around 0.3 mm/12 mil with standard 25 µm plating) carries roughly 1.5–1.8 A at a conservative 10 °C rise. Calculate the exact figure for your via with the tool above.
A via's copper is only the thin plated wall around the drilled hole (unless filled), so its actual copper cross-section is much smaller than the hole diameter might suggest — typically just tens of square mils for a common via size.
Vias sharing the current load in parallel approximately add their individual capacities: N identical vias can carry roughly N times a single via's rating, which is why designers use arrays under high-current connections.
This calculator finds how much electrical current the via's own copper can carry without overheating (a current-carrying / ampacity question). The Thermal Via calculator finds a via array's thermal resistance for spreading heat away from a hot component pad (a cooling / heat-spreading question). Both use the same via geometry but answer different questions.
A conductive-filled via has more copper cross-section than a hollow plated one, which would increase its current-carrying capacity in the same way it lowers thermal resistance — though filled vias are primarily specified for thermal or reliability reasons rather than current capacity alone.
Standard PCB manufacturing typically plates 20–35 µm (about 0.8–1.4 mils) of copper on the via wall, though some processes and specifications call for thicker plating for higher current or reliability requirements.
Divide your required current by the single-via current rating (from the calculator above) and round up, adding some margin for manufacturing tolerance and real-world non-ideal current sharing between vias — a common practice is to add at least one extra via beyond the bare minimum.
Both increase the annular copper area and therefore the current rating, but they interact differently with manufacturing cost and board density: increasing plating thickness affects all vias on the board (a process-wide choice), while individual via diameter can be chosen per application.
Yes — this calculator applies the identical I=k×ΔT0.44×A0.725 relationship, treating the via's annular copper cross-section the same way a trace's width×thickness cross-section is treated, which is standard industry practice for estimating via ampacity.
Not exactly — slight differences in via position, connecting trace length, and manufacturing variation mean current sharing is not perfectly even in practice. The N×single-via estimate is a good design guideline, but high-reliability designs often add margin beyond the bare calculated minimum.
At high frequencies, skin effect concentrates current toward the conductor surface, which can affect an unfilled via's effective resistance differently than at DC. This calculator addresses steady-state (DC/low-frequency) thermal current capacity; RF via design has additional considerations beyond ampacity.
Both work, and the choice is usually driven by other factors: a few larger vias take less board area and drilling operations, while many smaller vias may better match standard manufacturing capabilities and can spread current (and any single-via failure risk) more evenly.
Thermal Via Calculator • Trace Width Calculator • Trace Resistance & Voltage Drop • All Calculators